Fractional-N single-loop phase locked loop (PLL) synthesizers are often used for generating one frequency from a range of predetermined desirable frequencies. Typically this technique is performed for the purpose of transmitting or receiving a radio signal over one frequency channel of many possible allocations.
The structure of many fractional-N single-Loop PLL synthesizers is shown in FIG. 1. A voltage controlled oscillator (VCO) 10 provides an output signal 12, f.sub.o oscillating with a frequency responsive to a control signal 14, s2. A fractional-N divider 16 provides a divided signal 18, f.sub.d, such that the frequency of f.sub.i is the frequency of f divided by some desired division ration, N. A phase detector 20 provides a signal 22, s1, such that the signal 22, s1, is proportional to the phase or frequency difference between f.sub.d and a reference frequency signal 24, f.sub.r. A loop filter 26, F(s), provides the control signal 14, s2 so that the overall loop is a stable phase locked loop.
The output frequency 12, f.sub.o of such a synthesizer depends on the reference frequency 24, f.sub.r, and the desired division ration, N. Specifically, f.sub.o =Nf.sub.r.
Often a component of the fractional-N divider 16 is a delta-sigma modulator 26. In delta-sigma controlled synthesizers, the value of N can take on fractional values. Typically, this is provided by a programable divider 28, responsive to some programmed base value 30, n, and a first low resolution digital word 32, b.sub.i, of the delta-sigma modulator 26. A first summer 34 provides a control signal 36, c, such that the programmable divider 28 divides by predetermined ratios n, n+1, n+2, . . . n+k; where k is some predetermined integer which depends on the particular delta-sigma modulator 26 used. Various other means, known to those versed in the art, may be provided such that the delta-sigma modulator 26 selects one of the predetermined division ratios for each cycle of the programable divider 28.
Thus, if the delta-sigma modulator 26 has a fixed-point binary input 38, b.sub.ave, first low resolution digital word, 32, b.sub.i, for each cycle of the programmable divider 28, there is some time average value for this such that b.sub.i =b.sub.ave +Q.sub.i where b.sub.ave is the desired, fractional, average output and Q.sub.i is the quantization error for each cycle of the programmable divider 28. Since b.sub.ave is a long term average of many integers, it can have a fractional value and fractional-N division may be achieved.
In the short term, there is often an non-zero quantization error. A delta-sigma modulator 26 is defined herein by the ability to shape the spectral density of this quantization error. The noise shaping provided by the delta-sigma modulator 26 is such that the quantization error is reduced at and near to a frequency substantially equal to zero, the reference frequency 24, f.sub.r, and all multiples the reference frequency 24, f.sub.r.
This error shaping allows the quantization error to be substantially removed by the low pass filtering of the closed-loop PLL.
Although all delta-sigma modulators have the same functional definition, some delta-sigma modulators perform better than others in the ability to randomize and noise shape the quantization error. Some specific limitations are as follows.
With an input signal with a frequency substantially equal to zero, any digital delta-sigma modulator becomes a finite state machine. A delta-sigma modulator which has a longer sequence length, which in turn produces more spurious signals, will generally have less power in each individual spurious signal. The power in each of these spurious signals can presently limit the performance of a delta-sigma modulator based fractional-N synthesizer, especially when it is desirable to reduce the number of bits in the delta-sigma modulator. This creates difficulty in designing low power synthesizers with low spurious signals.
Another factor which limits the performance of delta-sigma modulator based fractional-N synthesizers is high frequency spurious signals outside the loop bandwidth of the PLL synthesizer. When these spurious signals are substantially larger than those produced by sequence length limits, any nonlinearity substantially equivalent to a phase detector nonlinearity can mix these spurious signals to new frequencies within the bandwidth of the PLL. These spurious signals often can not be filtered out by the loop filter.
Further, different delta-sigma modulators involve different amounts of digital hardware. In an large scale integration implementation, this hardware consumes silicon area and power, both of which are disadvantageous for low cost portable equipment.
For the foregoing reasons, there is a need to provide a fractional-N divider which uses a delta-sigma modulator with reduced spurious signals.